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SubjectRe: [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1
On Tue, Oct 24, 2017 at 01:32:51PM +0200, hpa@zytor.com wrote:
> On October 17, 2017 5:42:41 PM GMT+02:00, "Kirill A. Shutemov" <kirill@shutemov.name> wrote:
> >On Tue, Oct 03, 2017 at 11:27:54AM +0300, Kirill A. Shutemov wrote:
> >> On Fri, Sep 29, 2017 at 05:08:15PM +0300, Kirill A. Shutemov wrote:
> >> > The first bunch of patches that prepare kernel to boot-time
> >switching
> >> > between paging modes.
> >> >
> >> > Please review and consider applying.
> >>
> >> Ping?
> >
> >Ingo, is there anything I can do to get review easier for you?
> >
> >I hoped to get boot-time switching code into v4.15...
>
> One issue that has come up with this is what happens if the kernel is
> loaded above 4 GB and we need to switch page table mode. In that case
> we need enough memory below the 4 GB point to hold a root page table
> (since we can't write the upper half of cr3 outside of 64-bit mode) and
> a handful of instructions.
>
> We have no real way to know for sure what memory is safe without parsing
> all the memory maps and map out all the data structures that The
> bootloader has left for the kernel. I'm thinking that the best way to
> deal with this is to add an entry in setup_data to provide a pointers,
> with the kernel header specifying a necessary size and alignment.

I would appreciate your feedback on my take on this:

http://lkml.kernel.org/r/20171020195934.32108-1-kirill.shutemov@linux.intel.com

I don't change boot protocol, but trying to guess the safe spot in the way
similar to what we do for realmode trampoline.

--
Kirill A. Shutemov

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