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SubjectRe: [PATCHv2, RFC] x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G
On Mon, Oct 16, 2017 at 4:55 AM, Kirill A. Shutemov
<kirill@shutemov.name> wrote:
> On Sat, Oct 14, 2017 at 01:19:08PM -0400, Brian Gerst wrote:
>> From what we've seen with the TLB flush rework, having potential
>> garbage in the page tables that speculative reads can see can cause
>> bad things like machine checks. It would be best to have a second
>> temporary page just for the page table (and properly cleared).
>
> Hm. Interesting. Is there a place where I can read more about this?

I believe this thread was where it was first reported:
https://lkml.org/lkml/2017/9/5/152

>> The trampoline also needs its own stack, in case the stack pointer was
>> above 4G.
>
> You are right, we need new stack. I've missed that.
>
>> That could be at the end of the code page, since you only need 8 bytes.
>
> When I wrote about 8 bytes, I referred the usage of page table, not code.
> We use more than 8 bytes of code, but this should enough in the page.

What I meant was, on one page, have the code at the start of the page,
and the stack at the end. You only need 8 bytes of stack to push the
far pointer to return to 64-bit mode. The page table would be on the
second page.

--
Brian Gerst

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