Messages in this thread | | | From | Jassi Brar <> | Date | Fri, 13 Oct 2017 20:49:13 +0530 | Subject | Re: [PATCH v3 16/22] firmware: arm_scmi: add arm_mhu specific mailbox interface |
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On Fri, Oct 13, 2017 at 8:17 PM, Sudeep Holla <sudeep.holla@arm.com> wrote: > On 13/10/17 15:12, Jassi Brar wrote: > >> In MHU the 32bits are tied together and all go to one target >> processor. Whereas on QCom, each bit corresponds to independent signal >> going to a different target processor. >> > > I was not aware of that. Thanks for clarifying the differences. > >> IOW, QCom has 32 channels per register whereas MHU has one. The > > OK, that depends on how we consider it. As you said yes it just goes to > single target processor, but hardware designers consider it still 32 > channels are they can be controller independently without any locking. > MHU spec says it has three channels. Locking is not a criterion for a channel. A signal and associated data transfer defines a channel.
cheers
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