Messages in this thread | | | From | Shameerali Kolothum Thodi <> | Subject | RE: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon erratum 161010801 | Date | Wed, 25 Jan 2017 10:30:00 +0000 |
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> -----Original Message----- > From: Mark Rutland [mailto:mark.rutland@arm.com] > Sent: Tuesday, January 24, 2017 2:15 PM > To: Shameerali Kolothum Thodi > Cc: marc.zyngier@arm.com; will.deacon@arm.com; linux-arm- > kernel@lists.infradead.org; Linuxarm; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; John Garry; Guohanjun (Hanjun Guo); > robin.murphy@arm.com > Subject: Re: [RFC 2/4] irqchip, gicv3-its:Workaround for HiSilicon > erratum 161010801 sounds like this will have severe implications for virtualization. > > > Also these platforms doesn't have a proper IIDR > > register to use the existing IIDR based quirk mechanism. > > What exactly is wrong with the IIDR on these platforms? That sounds > like > an erratum as of itself. > > What precise value do reads of the IIDR return? Or do reads result in > other erroneous behaviour?
As far as I know, there is no erroneous behavior while reading. But the IIDR JEP106 identity code is 0 on these platforms, hence not much of use.
This will be corrected in next revision of hw.
Thanks, Shameer
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