Messages in this thread | | | From | Bharat Kumar Gogada <> | Subject | RE: [PATCH 3/4] PCI: Xilinx NWL: Modifying flow handler for legacy interrupts | Date | Tue, 24 Jan 2017 10:25:00 +0000 |
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> On 21/01/17 11:11, Bharat Kumar Gogada wrote: > > Legacy interrupts are level sensitive, so using handle_level_irq is > > more approprate as it is masks interrupts until End point handles > > interrupts and unmasks interrutps after End point handler is executed. > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> > > --- > > drivers/pci/host/pcie-xilinx-nwl.c | 2 +- > > 1 files changed, 1 insertions(+), 1 deletions(-) > > > > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c > > b/drivers/pci/host/pcie-xilinx-nwl.c > > index e1809f9..50f9c0d 100644 > > --- a/drivers/pci/host/pcie-xilinx-nwl.c > > +++ b/drivers/pci/host/pcie-xilinx-nwl.c > > @@ -433,7 +433,7 @@ static void nwl_unmask_leg_irq(struct irq_data > > *data) static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, > > irq_hw_number_t hwirq) > > { > > - irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_simple_irq); > > + irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); > > irq_set_chip_data(irq, domain->host_data); > > > > return 0; > > > > Please merge this patch and the following one in patch #2. There is no need for > going through equally broken intermediate steps. > Agreed, will merge it with second patch.
Thanks & Regards, Bharat
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