Messages in this thread | | | Date | Thu, 8 Sep 2016 13:50:23 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection |
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On Thu, Sep 08, 2016 at 02:57:01AM -0700, Fenghua Yu wrote: > From: Vikas Shivappa <vikas.shivappa@linux.intel.com> > > This patch includes CPUID enumeration routines for Cache allocation and > new values to track resources to the cpuinfo_x86 structure. > > Cache allocation provides a way for the Software (OS/VMM) to restrict > cache allocation to a defined 'subset' of cache which may be overlapping > with other 'subsets'. This feature is used when allocating a line in > cache ie when pulling new data into the cache. The programming of the > hardware is done via programming MSRs (model specific registers). > > Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com> > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> > Reviewed-by: Tony Luck <tony.luck@intel.com> > ---
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> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 92a8308..62d979b9 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -12,7 +12,7 @@ > /* > * Defines x86 CPU feature bits > */ > -#define NCAPINTS 18 /* N 32-bit words worth of info */ > +#define NCAPINTS 19 /* N 32-bit words worth of info */ > #define NBUGINTS 1 /* N 32-bit bug flags */ > > /* > @@ -220,6 +220,7 @@ > #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ > #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ > #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ > +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Director Technology */ > #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ > #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */ > #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ > @@ -286,6 +287,9 @@ > #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ > #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ > > +/* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 18 */
Seems like this leaf is dedicated to CAT and has only 2 feature bits defined in the SDM. Please use init_scattered_cpuid_features() instead of adding a whole CAP word.
-- Regards/Gruss, Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --
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