Messages in this thread | | | From | Linus Walleij <> | Date | Wed, 7 Sep 2016 16:59:17 +0200 | Subject | Re: [PATCH v3 8/8] gpio: Add Aspeed driver |
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On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> From: Joel Stanley <joel@jms.id.au> > > The Aspeed SoCs contain GPIOs banked by letter, where each bank contains > 8 pins. The GPIO banks are then grouped in sets of four in the register > layout. > > The implementation exposes multiple banks through the one driver and > requests and releases pins via the pinctrl subsystem. The hardware > supports generation of interrupts from all GPIO-capable pins. > > A number of hardware features are not yet supported: Configuration of > interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance > for output ports. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > Signed-off-by: Alistair Popple <alistair@popple.id.au> > Signed-off-by: Jeremy Kerr <jk@ozlabs.org> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Patch applied to the GPIO tree.
As there are no compile-time dependencies between the pin control and GPIO drivers I choose to merge the pinctrl stuff through the pinctrl tree and the GPIO stuff through the GPIO tree.
Yours, Linus Walleij
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