Messages in this thread | | | Subject | Re: [PATCH 6/6] ASoC: arizona: Add gating for source clocks of the FLLs | From | Sylwester Nawrocki <> | Date | Mon, 05 Sep 2016 10:12:10 +0200 |
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On 09/02/2016 05:52 PM, Charles Keepax wrote: > Whilst ultimately we would like to move all the clocking over to the > clock framework, as an intermediate step to get people going for now > enable the source clocks for FLLs as they are powered up. > > Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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