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    Subject[PATCH 4.4 110/192] [PATCH 114/135] drm/radeon/mst: fix regression in lane/link handling.
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit b36f7d26a7fdc0b07b1217368ee09bb8560269f8 ]

    The function this used changed in
    092c96a8ab9d1bd60ada2ed385cc364ce084180e
    drm/radeon: fix dp link rate selection (v2)

    However for MST we should just always train to the
    max link/rate. Though we probably need to limit this
    for future hw, in theory radeon won't support it.

    This fixes my 30" monitor with MST enabled.

    Cc: stable@vger.kernel.org # v4.4
    Signed-off-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/radeon/radeon_dp_mst.c | 12 ++----------
    1 file changed, 2 insertions(+), 10 deletions(-)

    --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
    +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
    @@ -525,17 +525,9 @@ static bool radeon_mst_mode_fixup(struct
    drm_mode_set_crtcinfo(adjusted_mode, 0);
    {
    struct radeon_connector_atom_dig *dig_connector;
    - int ret;
    -
    dig_connector = mst_enc->connector->con_priv;
    - ret = radeon_dp_get_dp_link_config(&mst_enc->connector->base,
    - dig_connector->dpcd, adjusted_mode->clock,
    - &dig_connector->dp_lane_count,
    - &dig_connector->dp_clock);
    - if (ret) {
    - dig_connector->dp_lane_count = 0;
    - dig_connector->dp_clock = 0;
    - }
    + dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
    + dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
    DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
    dig_connector->dp_lane_count, dig_connector->dp_clock);
    }

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