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    Subject[PATCH 4.4 51/68] perf/x86: fix PEBS issues on Intel Atom/Core2
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Stephane Eranian <eranian@google.com>

    commit 1424a09a9e1839285e948d4ea9fdfca26c9a2086 upstream.

    This patch fixes broken PEBS support on Intel Atom and Core2
    due to wrong pointer arithmetic in intel_pmu_drain_pebs_core().

    The get_next_pebs_record_by_bit() was called on PEBS format fmt0
    which does not use the pebs_record_nhm layout.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: kan.liang@intel.com
    Fixes: 21509084f999 ("perf/x86/intel: Handle multiple records in the PEBS buffer")
    Link: http://lkml.kernel.org/r/1449182000-31524-3-git-send-email-eranian@google.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/x86/kernel/cpu/perf_event_intel_ds.c | 9 ++++++++-
    1 file changed, 8 insertions(+), 1 deletion(-)

    --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
    @@ -1110,6 +1110,13 @@ get_next_pebs_record_by_bit(void *base,
    void *at;
    u64 pebs_status;

    + /*
    + * fmt0 does not have a status bitfield (does not use
    + * perf_record_nhm format)
    + */
    + if (x86_pmu.intel_cap.pebs_format < 1)
    + return base;
    +
    if (base == NULL)
    return NULL;

    @@ -1195,7 +1202,7 @@ static void intel_pmu_drain_pebs_core(st
    if (!event->attr.precise_ip)
    return;

    - n = (top - at) / x86_pmu.pebs_record_size;
    + n = top - at;
    if (n <= 0)
    return;


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