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Subject[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs
Date

This series fixes a small issue with the CPC driver when A CM3 is
present, where a redundant lock was taken.

There are then additions to the pm-cps driver to add support for R6 CPUs
such as the I6400, and additionally the CM3 present in the I6400.

Finally we enable the cpuidle-cps driver for MIPSr6 CPUs.

Applies atop v4.8-rc4



Matt Redfearn (10):
MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'
MIPS: CPC: Avoid lock when MIPS CM >= 3 is present
MIPS: pm-cps: Change FSB workaround to CPU blacklist
MIPS: pm-cps: Remove I6400 sync types
MIPS: pm-cps: Add P6600 implementation lightweight sync types
MIPS: pm-cps: Use MIPS standard lightweight ordering barrier
MIPS: pm-cps: Add MIPSr6 CPU support
MIPS: pm-cps: Support CM3 changes to Coherence Enable Register
MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other
cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.

arch/mips/include/asm/barrier.h | 10 ++++++
arch/mips/include/asm/mips-cm.h | 1 +
arch/mips/include/asm/pm-cps.h | 6 ++--
arch/mips/kernel/mips-cpc.c | 17 +++++++++--
arch/mips/kernel/pm-cps.c | 67 ++++++++++++++++++++++++-----------------
arch/mips/kernel/smp.c | 2 ++
drivers/cpuidle/Kconfig.mips | 2 +-
drivers/cpuidle/cpuidle-cps.c | 2 +-
8 files changed, 73 insertions(+), 34 deletions(-)

--
2.7.4

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