Messages in this thread | | | Date | Wed, 24 Aug 2016 16:55:14 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 |
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On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > While the Intel PMU monitors the LLC when perf enables the > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > L1 instruction cache fetches (0x0080) and instruction cache misses > (0x0081) on the AMD PMU. > > This is extremely confusing when monitoring the same workload across > Intel and AMD machines, since parameters like, > > $ perf stat -e cache-references,cache-misses > > measure completely different things. > > Instead, make the AMD PMU measure instruction/data cache and TLB fill > requests to the L2 and instruction/data cache and TLB misses in the L2 > when HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled, > respectively. That way the events measure unified caches on both > platforms.
I'm still not really sure about this: we can't really compare L3 to L2 access patterns - it is almost as comparing apples to oranges. Can we use the Intel L2 events instead?
I mean, this makes much more sense to me because:
* you *actually* compare the same cache levels * you have L2 *everywhere* vs L3 (and L4) which are sometimes not present on thin clients
People who want LLC can enable them with -e additionally...
Hmmm.
-- Regards/Gruss, Boris.
ECO tip #101: Trim your mails when you reply. --
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