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SubjectRe: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write
2016-08-09 2:16 GMT+08:00 Radim Krčmář <>:
> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
> write with vmcs02 as the current VMCS.
> This will incorrectly apply modifications intended for vmcs01 to vmcs02
> and L2 can use it to gain access to L0's x2APIC registers by disabling
> virtualized x2APIC while using msr bitmap that assumes enabled.
> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
> current VMCS. An alternative solution would temporarily make vmcs01 the
> current VMCS, but it requires more care.

There is a scenario both L1 and L2 are running on x2apic mode, L1
don't own the APIC_BASE writes, then L2 is intended to disable x2apic
mode, however, your logic will also disable x2apic mode for L1.

Wanpeng Li

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