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SubjectRe: [RFC PATCH v1] irqchip: add support for SMP irq router
On 06/07/16 11:47, Sebastian Frias wrote:

>>> I think I'm missing something, what is the difference between the domains
>>> described by nodes in the DT for irq-tango.c (arch/arm/boot/dts/tango4-common.dtsi)
>>> and the DT from my RFC?
>> The fundamental difference is that with your new fancy controller, you
>> can decide what is going where, while the previous one is completely set
>> in stone (the output line is a direct function of the input line).
> I think that's where part the misunderstanding comes from.
> IMHO the output line is not a direct function of the input line.
> Any of the 64 IRQ lines entering the "old controller" (irq-tango.c) can be
> routed to any of its 3 outputs.

Then the current DT binding isn't properly describing the HW.

> The only thing fixed is which GIC input is connected to those 3 outputs, ie:
> GIC inputs 2, 3 and 4.
> In the the "new controller" (irq-tango_v2.c, this RFC), any of 128 IRQ lines
> can be routed to any of 24 outputs, connected to GIC inputs 0...23.
> In a nutshell:
> - "old controller": routes [0...N] => GIC inputs [2...4]
> - "new controller": routes [0...M] => GIC inputs [0...23]
> So, when we think about it, if the "new DT" specified 24 domains, it would
> be equivalent of the "old DT" with 3 domains, right?

Indeed, but I consider the "old" binding to be rather misleading. It
should have been described as a router too, rather than hardcoding
things in DT. Granted, it doesn't matter much when you only have 3
possible output lines. But with 24 outputs, that becomes much more relevant.

> That's why it seemed more or less natural to keep describing the domains in
> the DT, the main reason for that being that it allowed the user to specify
> the IRQ sharing in the DT, and this is precisely the key point of this.
> So, putting aside routing considerations and the discussion above, I think
> a simpler question is: if the domains should not be described in the DT,
> how can we define the IRQ sharing in the DT?

You could have a set of sub-nodes saying something like this:

mux-hint0 {
inputs = <1 45 127>;

mux-hint1 {
inputs = <2 33>;

(or maybe you can have that as direct properties, but you get the idea).
Here, you have two output pins dedicated to muxed interrupts (assuming
they are all level interrupts), and the last 22 can be freely allocated
as direct routes.


Jazz is not dead. It just smells funny...

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