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SubjectRE: [PATCH 1/1] EDAC, sb_edac: Fix channel reporting on Knights Landing
On Saturday, July 23, 2016 1:45 AM, Lukasz Odzioba wrote:
> On Intel Xeon Phi Knights Landing processor family the channels
> of memory controller have untypical arrangement - MC0 is mapped to
> CH3,4,5 and MC1 is mapped to CH0,1,2. This causes EDAC driver to
> report the channel name incorrectly.
> We missed this change earlier, so the code already contains
> similar comment, but the translation function is incorrect.
> Without this patch:
> errors in DIMM_A and DIMM_D were reported in DIMM_D
> errors in DIMM_B and DIMM_E were reported in DIMM_E
> errors in DIMM_C and DIMM_F were reported in DIMM_F
> Fixes: d0cdf9003140 ("sb_edac: Add Knights Landing (Xeon Phi gen 2) support")

I would greatly appreciate it if you kindly give me some feedback on this patch.


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