| From | Arnaldo Carvalho de Melo <> | Subject | [PATCH 46/66] perf tools: Fallback to reading sysfs to get cacheline size | Date | Tue, 12 Jul 2016 19:40:21 -0300 |
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From: Arnaldo Carvalho de Melo <acme@redhat.com>
On systems where sysconf(_SC_LEVEL1_DCACHE_LINESIZE) is not available, such as musl LIBC and Android's bionic libc.
Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Chris Phlipot <cphlipot0@gmail.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Wang Nan <wangnan0@huawei.com> Link: http://lkml.kernel.org/n/tip-772obxzby758g7m2wmzcejxz@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> --- tools/perf/perf.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/tools/perf/perf.c b/tools/perf/perf.c index f7d7dbbd2af6..4b2ff021434c 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -497,6 +497,16 @@ void pthread__unblock_sigwinch(void) pthread_sigmask(SIG_UNBLOCK, &set, NULL); } +#ifdef _SC_LEVEL1_DCACHE_LINESIZE +#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) +#else +static void cache_line_size(int *cacheline_sizep) +{ + if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep)) + perror("cannot determine cache line size"); +} +#endif + int main(int argc, const char **argv) { const char *cmd; @@ -509,7 +519,7 @@ int main(int argc, const char **argv) /* The page_size is placed in util object. */ page_size = sysconf(_SC_PAGE_SIZE); - cacheline_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); + cache_line_size(&cacheline_size); if (sysctl__read_int("kernel/perf_event_max_stack", &value) == 0) sysctl_perf_event_max_stack = value; -- 2.7.4
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