lkml.org 
[lkml]   [2016]   [Jul]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: [PATCH v2 18/22] usb: chipidea: msm: Add reset controller for PHY POR bit
On 10 July 2016 at 22:32, Peter Chen <hzpeterchen@gmail.com> wrote:
> On Thu, Jul 07, 2016 at 03:21:09PM -0700, Stephen Boyd wrote:
>> @@ -40,11 +43,38 @@ struct ci_hdrc_msm {
>> struct clk *iface_clk;
>> struct clk *fs_clk;
>> struct ci_hdrc_platform_data pdata;
>> + struct reset_controller_dev rcdev;
>> bool secondary_phy;
>> bool hsic;
>> void __iomem *base;
>> };
>>
>> +static int
>> +ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
>> +{
>> + struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
>> + void __iomem *addr = ci_msm->base;
>> + u32 val;
>> +
>> + if (id)
>> + addr += HS_PHY_SEC_CTRL;
>> + else
>> + addr += HS_PHY_CTRL;
>> +
>> + val = readl_relaxed(addr);
>> + val |= HS_PHY_POR_ASSERT;
>> + writel(val, addr);
>> + udelay(12);
>
> Does this delay is reference manual defines or experienced value?
> Do you need to comment it?
>

10us comes from the manual but we add two more from experience. I can
add a comment to that effect similar to the one above udelay(12) in
phy-msm-usb.c?

\
 
 \ /
  Last update: 2016-07-12 01:01    [W:0.052 / U:4.176 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site