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Subject[tip:x86/timers] x86/tsc_msr: Extend to include Intel Core Architecture
Commit-ID:  fc273eeef314cdaf0ac992b400d126f8184a4d1c
Gitweb: http://git.kernel.org/tip/fc273eeef314cdaf0ac992b400d126f8184a4d1c
Author: Len Brown <len.brown@intel.com>
AuthorDate: Fri, 17 Jun 2016 01:22:49 -0400
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Sun, 10 Jul 2016 17:00:13 +0200

x86/tsc_msr: Extend to include Intel Core Architecture

tsc_msr is used to quickly and reliably
enumerate the CPU/TSC frequencies at boot time
For the Intel Atom Architecture.

Extend tsc_msr to include recent Intel Core Architecture.

As this code discovers BCLK, it also sets lapic_timer_frequency,
which allows LAPIC timer calibration to be skipped,
though it is already skipped on systems with a TSC deadline timer.

Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/8c82d5a94b754b6015f8cf8ea1fde15821fc6611.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/tsc_msr.c | 49 +++++++++++++++++++++++++++++++++++++++--------
1 file changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 65b3d8cb..9d56ebd 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -77,23 +77,56 @@ unsigned long try_msr_calibrate_tsc(void)
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return 0;

+ /*
+ * 100 MHz BCLK Core Architecture -- before SKL.
+ * De-rate 100Mhz by about 0.25% to account
+ * for the average effect of spread-spectrum clocking.
+ */
+ switch (boot_cpu_data.x86_model) {
+
+ case 0x2A: /* SNB */
+ case 0x3A: /* IVB */
+ freq = 99773;
+ goto get_ratio;
+ case 0x2D: /* SNB Xeon */
+ case 0x3E: /* IVB Xeon */
+ freq = 99760;
+ goto get_ratio;
+ case 0x3C: /* HSW */
+ case 0x3F: /* HSW */
+ case 0x45: /* HSW */
+ case 0x46: /* HSW */
+ case 0x3D: /* BDW */
+ case 0x47: /* BDW */
+ case 0x4F: /* BDX */
+ case 0x56: /* BDX-DE */
+ freq = 99769;
+ goto get_ratio;
+ }
+
+ /*
+ * Atom Architecture
+ */
cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
if (cpu_index < 0)
return 0;

- if (freq_desc_tables[cpu_index].msr_plat) {
- rdmsr(MSR_PLATFORM_INFO, lo, hi);
- ratio = (lo >> 8) & 0xff;
- } else {
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- ratio = (hi >> 8) & 0x1f;
- }
-
/* Get FSB FREQ ID */
rdmsr(MSR_FSB_FREQ, lo, hi);
freq_id = lo & 0x7;
freq = id_to_freq(cpu_index, freq_id);

+ if (!freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi >> 8) & 0x1f;
+ goto done;
+ }
+
+get_ratio:
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo >> 8) & 0xff;
+
+done:
/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
res = freq * ratio;

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