Messages in this thread | | | Date | Thu, 30 Jun 2016 10:31:08 +0200 | From | Jean-Francois Moine <> | Subject | Re: [PATCH v3 13/14] clk: sunxi-ng: Add H3 clocks |
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On Wed, 29 Jun 2016 21:05:34 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> +static void __init sun8i_h3_ccu_setup(struct device_node *node) > +{ > + void __iomem *reg; > + u32 val; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + if (IS_ERR(reg)) { > + pr_err("%s: Could not map the clock registers\n", > + of_node_full_name(node)); > + return; > + } > + > + /* Force the PLL-Audio-1x divider to 4 */ > + val = readl(reg + SUN8I_H3_PLL_AUDIO_REG); > + val &= ~GENMASK(4, 0); > + writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG); > + > + sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc); > +}
FYI, the pll-audio PLL_POST_DIV is 19:16.
-- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
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