Messages in this thread | | | Date | Mon, 20 Jun 2016 17:48:46 -0700 | From | Stephen Boyd <> | Subject | Re: [PATCH v2 2/2] clk: vt8500: rework wm8650_find_pll_bits() |
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On 06/08, Roman Volkov wrote: > From: Roman Volkov <rvolkov@v1ros.org> > > PLL clock on WM8650 is calculated in the following way: > > M * parent [O1] => / P [O2] => / D [O3] > > Where O2 is 600MHz >= (M * parent) / P >= 300MHz. > > Current algorithm does not met this requirement, so that the > function may return rates which are not supported by the hardware. > > This patch fixes the algorithm and simplifies the code, reducing > the calculation time by ~10000 times (according to usermode app) by > removing the nested loops. > > Signed-off-by: Roman Volkov <rvolkov@v1ros.org> > ---
Applied to clk-next
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