Messages in this thread | | | Subject | Re: [PATCH 02/13] irq: Introduce IRQD_AFFINITY_MANAGED flag | From | Bart Van Assche <> | Date | Wed, 15 Jun 2016 22:50:53 +0200 |
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On 06/15/2016 10:12 PM, Keith Busch wrote: > On Wed, Jun 15, 2016 at 04:06:55PM -0400, Keith Busch wrote: >>> >>> 0: A0 B0 >>> 1: A1 B1 >>> 2: A2 B2 >>> 3: A3 B3 >>> 4: A4 B4 >>> 5: A5 B5 >>> 6: A6 B6 >>> 7: A7 B7 >>> 8: (none) >>> ... >>> 31: (none) >> >> I'll need to look at the follow on patches do to confirm, but that's >> not what this should do. All CPU's should have a vector assigned because >> every CPU needs to be assigned a submission context using a vector. In >> your example, every vector's affinity mask should be assigned to 4 CPUs: >> vector '8' starts over with A0 B0, '9' gets A1 B1, and so on. > > ^^^^^^ > > Sorry, I meant "CPU '8'", not "vector '8'".
Hello Keith,
Does it matter on x86 systems whether or not these interrupt vectors are also associated with a CPU with a higher CPU number? Although multiple bits can be set in /proc/irq/<n>/smp_affinity only the first bit counts on x86 platforms. In default_cpu_mask_to_apicid_and() it is easy to see that only the first bit that has been set in that mask counts on x86 systems.
Bart.
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