Messages in this thread Patch in this message | | | Subject | [PATCH 5/5] x86, msr: use Intel family macros for msr events code | From | Dave Hansen <> | Date | Wed, 01 Jun 2016 10:34:46 -0700 |
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From: Dave Hansen <dave.hansen@linux.intel.com>
Use the new INTEL_FAM6_MODEL_* macros for arch/x86/events/msr.c.
This code appears to be missing handling for "WESTMERE2" and "SKYLAKE_X".
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> ---
b/arch/x86/events/msr.c | 59 ++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 29 deletions(-)
diff -puN arch/x86/events/msr.c~x86-intel-familites-msr arch/x86/events/msr.c --- a/arch/x86/events/msr.c~x86-intel-familites-msr 2016-06-01 10:20:12.546391511 -0700 +++ b/arch/x86/events/msr.c 2016-06-01 10:20:12.550391692 -0700 @@ -1,4 +1,5 @@ #include <linux/perf_event.h> +#include <asm/intel-family.h> enum perf_msr_id { PERF_MSR_TSC = 0, @@ -34,39 +35,39 @@ static bool test_intel(int idx) return false; switch (boot_cpu_data.x86_model) { - case 30: /* 45nm Nehalem */ - case 26: /* 45nm Nehalem-EP */ - case 46: /* 45nm Nehalem-EX */ - - case 37: /* 32nm Westmere */ - case 44: /* 32nm Westmere-EP */ - case 47: /* 32nm Westmere-EX */ - - case 42: /* 32nm SandyBridge */ - case 45: /* 32nm SandyBridge-E/EN/EP */ - - case 58: /* 22nm IvyBridge */ - case 62: /* 22nm IvyBridge-EP/EX */ - - case 60: /* 22nm Haswell Core */ - case 63: /* 22nm Haswell Server */ - case 69: /* 22nm Haswell ULT */ - case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */ - - case 61: /* 14nm Broadwell Core-M */ - case 86: /* 14nm Broadwell Xeon D */ - case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */ - case 79: /* 14nm Broadwell Server */ - - case 55: /* 22nm Atom "Silvermont" */ - case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */ - case 76: /* 14nm Atom "Airmont" */ + case INTEL_FAM6_MODEL_NEHALEM: + case INTEL_FAM6_MODEL_NEHALEM_EP: + case INTEL_FAM6_MODEL_NEHALEM_EX: + + case INTEL_FAM6_MODEL_WESTMERE: + case INTEL_FAM6_MODEL_WESTMERE_EP: + case INTEL_FAM6_MODEL_WESTMERE_EX: + + case INTEL_FAM6_MODEL_SANDYBRIDGE: + case INTEL_FAM6_MODEL_SANDYBRIDGE_X: + + case INTEL_FAM6_MODEL_IVYBRIDGE: + case INTEL_FAM6_MODEL_IVYBRIDGE_X: + + case INTEL_FAM6_MODEL_HASWELL_CORE: + case INTEL_FAM6_MODEL_HASWELL_X: + case INTEL_FAM6_MODEL_HASWELL_ULT: + case INTEL_FAM6_MODEL_HASWELL_GT3E: + + case INTEL_FAM6_MODEL_BROADWELL_CORE_M: + case INTEL_FAM6_MODEL_BROADWELL_XEON_D: + case INTEL_FAM6_MODEL_BROADWELL_GT3E: + case INTEL_FAM6_MODEL_BROADWELL_X: + + case INTEL_FAM6_MODEL_ATOM_SILVERMONT1: + case INTEL_FAM6_MODEL_ATOM_SILVERMONT2: + case INTEL_FAM6_MODEL_ATOM_AIRMONT: if (idx == PERF_MSR_SMI) return true; break; - case 78: /* 14nm Skylake Mobile */ - case 94: /* 14nm Skylake Desktop */ + case INTEL_FAM6_MODEL_SKYLAKE_MOBILE: + case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; _
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