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    Subject[PATCH 4.2.y-ckt 03/59] ASoC: rt5640: Correct the digital interface data select
    Date
    4.2.8-ckt10 -stable review patch.  If anyone has any objections, please let me know.

    ---8<------------------------------------------------------------

    From: Sugar Zhang <sugar.zhang@rock-chips.com>

    commit 653aa4645244042826f105aab1be3d01b3d493ca upstream.

    this patch corrects the interface adc/dac control register definition
    according to datasheet.

    Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Kamal Mostafa <kamal@canonical.com>
    ---
    sound/soc/codecs/rt5640.c | 2 +-
    sound/soc/codecs/rt5640.h | 36 ++++++++++++++++++------------------
    2 files changed, 19 insertions(+), 19 deletions(-)

    diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
    index ff72cd8..78624e8 100644
    --- a/sound/soc/codecs/rt5640.c
    +++ b/sound/soc/codecs/rt5640.c
    @@ -360,7 +360,7 @@ static unsigned int bst_tlv[] = {

    /* Interface data select */
    static const char * const rt5640_data_select[] = {
    - "Normal", "left copy to right", "right copy to left", "Swap"};
    + "Normal", "Swap", "left copy to right", "right copy to left"};

    static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
    RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
    diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
    index 3deb8ba..243f426 100644
    --- a/sound/soc/codecs/rt5640.h
    +++ b/sound/soc/codecs/rt5640.h
    @@ -442,39 +442,39 @@
    #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
    #define RT5640_IF1_DAC_SEL_SFT 14
    #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
    -#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)
    -#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)
    -#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)
    +#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
    +#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
    +#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
    #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
    #define RT5640_IF1_ADC_SEL_SFT 12
    #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
    -#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)
    -#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)
    -#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)
    +#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
    +#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
    +#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
    #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
    #define RT5640_IF2_DAC_SEL_SFT 10
    #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
    -#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)
    -#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)
    -#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)
    +#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
    +#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
    +#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
    #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
    #define RT5640_IF2_ADC_SEL_SFT 8
    #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
    -#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)
    -#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)
    -#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)
    +#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
    +#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
    +#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
    #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
    #define RT5640_IF3_DAC_SEL_SFT 6
    #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
    -#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)
    -#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)
    -#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)
    +#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
    +#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
    +#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
    #define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
    #define RT5640_IF3_ADC_SEL_SFT 4
    #define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
    -#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)
    -#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)
    -#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)
    +#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
    +#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4)
    +#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4)

    /* REC Left Mixer Control 1 (0x3b) */
    #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
    --
    2.7.4
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