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    Subject[PATCH v2 02/32] perf/x86/intel/cqm: software cache for MSR_IA32_PQR_ASSOC
    Date
    The msr MSR_IA32_PQR_ASSOC is shared by CQM and the upcoming CAT. Since
    writes to this msr are slow (more than 1000 cycles) and mostly occur in
    context switch, this patch introduces a software cache that avoids wrsmr
    that wont change the msr's value.

    Reviewed-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
    ---
    arch/x86/include/asm/pqr_common.h | 44 +++++++++++++++++++++++++++++++++++++++
    arch/x86/kernel/cpu/pqr_common.c | 8 +++++++
    2 files changed, 52 insertions(+)
    create mode 100644 arch/x86/include/asm/pqr_common.h
    create mode 100644 arch/x86/kernel/cpu/pqr_common.c

    diff --git a/arch/x86/include/asm/pqr_common.h b/arch/x86/include/asm/pqr_common.h
    new file mode 100644
    index 0000000..854febe
    --- /dev/null
    +++ b/arch/x86/include/asm/pqr_common.h
    @@ -0,0 +1,44 @@
    +#ifndef _X86_PQR_COMMON_H_
    +#define _X86_PQR_COMMON_H_
    +
    +#if defined(CONFIG_INTEL_RDT)
    +
    +#include <linux/types.h>
    +#include <asm/percpu.h>
    +#include <asm/msr.h>
    +
    +#define MSR_IA32_PQR_ASSOC 0x0c8f
    +
    +#define INVALID_RMID (-1)
    +
    +/**
    + * struct intel_pqr_state - State cache for the PQR MSR
    + * @rmid: The cached Resource Monitoring ID
    + * @closid: The cached Class Of Service ID
    + *
    + * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
    + * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
    + * contains both parts, so we need to cache them.
    + *
    + * The cache also helps to avoid pointless updates if the value does
    + * not change.
    + */
    +struct intel_pqr_state {
    + u32 rmid;
    + u32 closid;
    +};
    +
    +DECLARE_PER_CPU(struct intel_pqr_state, pqr_state);
    +
    +static inline void pqr_update_rmid(u32 rmid)
    +{
    + struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
    +
    + if (state->rmid == rmid)
    + return;
    + state->rmid = rmid;
    + wrmsr(MSR_IA32_PQR_ASSOC, rmid, state->closid);
    +}
    +
    +#endif
    +#endif
    diff --git a/arch/x86/kernel/cpu/pqr_common.c b/arch/x86/kernel/cpu/pqr_common.c
    new file mode 100644
    index 0000000..dc6debc
    --- /dev/null
    +++ b/arch/x86/kernel/cpu/pqr_common.c
    @@ -0,0 +1,8 @@
    +#include <asm/pqr_common.h>
    +
    +/*
    + * The cached intel_pqr_state is strictly per CPU and can never be
    + * updated from a remote CPU. Functions that modify pqr_state
    + * must ensure interruptions are properly handled.
    + */
    +DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
    --
    2.8.0.rc3.226.g39d4020
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