Messages in this thread | | | Date | Wed, 11 May 2016 11:24:00 +0200 | Subject | Re: [PATCH V2] pinctrl: tegra: Correctly check the supported configuration | From | Linus Walleij <> |
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On Mon, May 2, 2016 at 7:23 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> The pincontrol registers of Tegra chips has multiple filed per > registers. There is two type of registers mux and drive. All > configurations belongs to one of these registers. > > If any configurations are supported then <config>_bit is set to > bit position of these registers otherwise -1 to not support it. > The member is defined as > s32 <config>_bit:6; > > So if config is not supported ifor given SoC then it is set to -1 > in soc pinmmux table. > In common driver code, to find out that given config is supported > or not, it is checked as: > > s8 bit = <config>_bit; > if (bit > 31) { > /* Not supported config */ > } > > But in this case, bit is s8 and hence for non supporting it is -1. > > Correct the check as: > if (bit < 0) { > /* Not supported config */ > } > > Fixes: e4c02dced975cb ("pinctrl: tegra: use signed bitfields for optional fields") > Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Patch applied with Stephen's ACK.
Yours, Linus Walleij
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