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SubjectRe: [PATCH v2] OMAPDSS: HDMI5: Change DDC timings
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On 21/04/16 20:27, J.D. Schroeder wrote:
> From: Jim Lodes <jim.lodes@garmin.com>
>
> The DDC scl high and low times were set to the minimum values
> from the i2c specification, but the i2c specification takes into
> account the rise time and fall time to calculate the frequency.
> To pass HDMI certification DDC can not exceed 100kHz therefore in
> a system where the rise times and fall times are negligible the high
> and low times for scl need to be 10us.
>
> Signed-off-by: Jim Lodes <jim.lodes@garmin.com>
> Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com>
> ---
> drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++--
> drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)

Thanks! Queuing this for 4.7.

Tomi

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