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SubjectRe: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration
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On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni
<gabriele.paoloni@huawei.com> wrote:
>
> Currently dw_pcie_setup_rc configures memory base and memory
> limit in the type1 configuration header for the root complex.
> In doing so it uses the cpu address (pp->mem_base) rather than
> the bus address (pp->mem_bus_addr): this is wrong and it is
> useless since the configuration is overwritten later on when
> pci_bus_assign_resources() is called.
>
> Therefore this patch just removes this configuration from
> dw_pcie_setup_rc.
>
> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>

Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

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