Messages in this thread | | | Date | Tue, 19 Apr 2016 11:16:05 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible |
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On Fri, Apr 15, 2016 at 03:29:11PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The Allwinner SoCs have a gate controller to gate the access to the DRAM > > clock to the some devices that need to access the DRAM directly (mostly > > display / image related IPs). > > > > Use a simple gates driver to support the one found in the A13 / R8 SoCs. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Acked-by: Chen-Yu Tsai <wens@csie.org> > > Acked-by: Rob Herring <robh@kernel.org> > > --- > > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Applied, thanks! Maxime
-- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [unhandled content-type:application/pgp-signature] | |