Messages in this thread |  | | Date | Fri, 15 Apr 2016 16:03:32 +0200 | | Subject | Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads | | From | Linus Walleij <> |
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On Fri, Apr 15, 2016 at 1:47 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote: > On Friday 15 April 2016 04:45 PM, Linus Walleij wrote: >> On Fri, Apr 15, 2016 at 11:55 AM, Laxman Dewangan <ldewangan@nvidia.com> >> wrote:
>> But to be sure we would like to know what is actually happening, >> electronically speaking, when you set this up. Do you have any >> idea? > > From electronic point of view, the value of VIL, VIH, VOL, VOH (Input/output > voltage level for low and high state) are different when talking for 0 t > 1.8V and 0 to 3.3V.
Yeah that I get. But since it is switched on a per-pin basis, and this is not about what voltage is actually supplied to the I/O cell, because that comes from the outside, it is a mystery why it is even needed.
I understand that there is a bit selecting driving voltage level in the register range, what I don't understand is what that is doing in the I/O cell.
The bit in the register must be routed to somehing in the I/O cell and I would like to know what. I take it that an ordinary CMOS totem-pole push-pull output is going to work the same with 1.8 and 3.3V alike so it's obviously not enabling any extra transistors or anything.
Yours, Linus Walleij
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