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    Subject[PATCH 3.13.y-ckt 11/43] iommu/amd: Fix boot warning when device 00:00.0 is not iommu covered
    Date
    3.13.11-ckt37 -stable review patch.  If anyone has any objections, please let me know.

    ---8<------------------------------------------------------------

    From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>

    commit 38e45d02ea9f194b89d6bf41e52ccafc8e2c2b47 upstream.

    The setup code for the performance counters in the AMD IOMMU driver
    tests whether the counters can be written. It tests to setup a counter
    for device 00:00.0, which fails on systems where this particular device
    is not covered by the IOMMU.

    Fix this by not relying on device 00:00.0 but only on the IOMMU being
    present.

    Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    Signed-off-by: Kamal Mostafa <kamal@canonical.com>
    ---
    drivers/iommu/amd_iommu_init.c | 34 ++++++++++++++++++++++------------
    1 file changed, 22 insertions(+), 12 deletions(-)

    diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
    index 8f798be..9afa397 100644
    --- a/drivers/iommu/amd_iommu_init.c
    +++ b/drivers/iommu/amd_iommu_init.c
    @@ -227,6 +227,10 @@ static enum iommu_init_state init_state = IOMMU_START_STATE;
    static int amd_iommu_enable_interrupts(void);
    static int __init iommu_go_to_state(enum iommu_init_state state);

    +static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
    + u8 bank, u8 cntr, u8 fxn,
    + u64 *value, bool is_write);
    +
    static inline void update_last_devid(u16 devid)
    {
    if (devid > amd_iommu_last_bdf)
    @@ -1183,8 +1187,8 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu)
    amd_iommu_pc_present = true;

    /* Check if the performance counters can be written to */
    - if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
    - (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
    + if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
    + (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
    (val != val2)) {
    pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
    amd_iommu_pc_present = false;
    @@ -2315,22 +2319,15 @@ u8 amd_iommu_pc_get_max_counters(u16 devid)
    }
    EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);

    -int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
    +static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
    + u8 bank, u8 cntr, u8 fxn,
    u64 *value, bool is_write)
    {
    - struct amd_iommu *iommu;
    u32 offset;
    u32 max_offset_lim;

    - /* Make sure the IOMMU PC resource is available */
    - if (!amd_iommu_pc_present)
    - return -ENODEV;
    -
    - /* Locate the iommu associated with the device ID */
    - iommu = amd_iommu_rlookup_table[devid];
    -
    /* Check for valid iommu and pc register indexing */
    - if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
    + if (WARN_ON((fxn > 0x28) || (fxn & 7)))
    return -ENODEV;

    offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
    @@ -2354,3 +2351,16 @@ int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
    return 0;
    }
    EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
    +
    +int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
    + u64 *value, bool is_write)
    +{
    + struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
    +
    + /* Make sure the IOMMU PC resource is available */
    + if (!amd_iommu_pc_present || iommu == NULL)
    + return -ENODEV;
    +
    + return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
    + value, is_write);
    +}
    --
    2.7.0
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