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SubjectRe: [PATCH V7 11/12] arm64: tegra: add soctherm node for Tegra210
On Tue, Mar 15, 2016 at 06:43:00PM +0800, Wei Ni wrote:
>
>
> On 2016年03月15日 03:25, Eduardo Valentin wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Mar 11, 2016 at 11:11:34AM +0800, Wei Ni wrote:
> >> Adds soctherm node for Tegra210, and add cpu,
> >> gpu, mem, pllx as thermal-zones. Set critical
> >> trip temp for cpu and gpu thermal zone.
> >>
> >> Signed-off-by: Wei Ni <wni@nvidia.com>
> >> ---
> >> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 60 ++++++++++++++++++++++++++++++++
> >> 1 file changed, 60 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> >> index cd4f45ccd6a7..c7ef500a347e 100644
> >> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> >> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> >> @@ -3,6 +3,7 @@
> >> #include <dt-bindings/memory/tegra210-mc.h>
> >> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/thermal/tegra124-soctherm.h>
> >>
> >> / {
> >> compatible = "nvidia,tegra210";
> >> @@ -802,4 +803,63 @@
> >> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> >> interrupt-parent = <&gic>;
> >> };
> >> +
> >> + soctherm: thermal-sensor@0,700e2000 {
> >> + compatible = "nvidia,tegra210-soctherm";
> >> + reg = <0x0 0x700e2000 0x0 0x1000>;
> >> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
> >> + <&tegra_car TEGRA210_CLK_SOC_THERM>;
> >> + clock-names = "tsensor", "soctherm";
> >> + resets = <&tegra_car 78>;
> >> + reset-names = "soctherm";
> >> + #thermal-sensor-cells = <1>;
> >> + };
> >> +
> >> + thermal-zones {
> >> + cpu {
> >> + polling-delay-passive = <1000>;
> >> + polling-delay = <0>;
> >> +
> >> + thermal-sensors =
> >> + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
> >> +
> >> + trips {
> >> + cpu_shutdown_trip: shutdown-trip {
> >> + temperature = <102500>;
> >> + hysteresis = <1000>;
> >> + type = "critical";
> >> + };
> >> + };
> >> + };
> >> + mem {
> >> + polling-delay-passive = <0>;
> >> + polling-delay = <0>;
> >> +
> >> + thermal-sensors =
> >> + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
> >
> >
> > Why no trips for mem? Why should we care ?
>
> The critical trip temperature will be set to HW for critical shutdown. Normally,
> we just take care the CPU and GPU temperature. And in HW, the MEM use the same
> critical trip with GPU. For PLLX, we just keep the default critical trip in HW.
> So I didn't configure the MEM and PLLX. I can add critical trips for them.

Ok. Please add them.

>
> >
> > Please have a look on the binding to check for mandatory properties and
> > sub nodes.
>
> Hmm, yes, the trips and cooling-maps are required properties. How about to add a
> dummy-cool-dev, so that it could be compatible with the binding.
>

Yeah, what people are doing, when the cooling devices are not ready to
be linked, is to add an empty section of cooling-maps.


> Wei.
>
> >
> >> + };
> >> + gpu {
> >> + polling-delay-passive = <1000>;
> >> + polling-delay = <0>;
> >> +
> >> + thermal-sensors =
> >> + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
> >> +
> >> + trips {
> >> + gpu_shutdown_trip: shutdown-trip {
> >> + temperature = <103000>;
> >> + hysteresis = <1000>;
> >> + type = "critical";
> >> + };
> >> + };
> >> + };
> >> + pllx {
> >> + polling-delay-passive = <0>;
> >> + polling-delay = <0>;
> >> +
> >> + thermal-sensors =
> >> + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
> >
> > ditto
> >
> >> + };
> >> + };
> >> };
> >> --
> >> 1.9.1
> >>
> >
> > * Unknown Key
> > * 0x7DA4E256
> >
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