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    Subject[PATCH v8 17/23] powerpc/8xx: rewrite flush_instruction_cache() in C
    Date
    On PPC8xx, flushing instruction cache is performed by writing
    in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
    The patch rewrites the fonction in C so that CPU6 ERRATA will
    be handled transparently

    Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
    ---
    v2: no change
    v3: no change
    v4: no change
    v5: no change
    v6: no change
    v8: no change

    arch/powerpc/kernel/misc_32.S | 10 ++++------
    arch/powerpc/mm/8xx_mmu.c | 7 +++++++
    2 files changed, 11 insertions(+), 6 deletions(-)

    diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
    index be8edd6..7d1284f 100644
    --- a/arch/powerpc/kernel/misc_32.S
    +++ b/arch/powerpc/kernel/misc_32.S
    @@ -296,12 +296,9 @@ _GLOBAL(real_writeb)
    * Flush instruction cache.
    * This is a no-op on the 601.
    */
    +#ifndef CONFIG_PPC_8xx
    _GLOBAL(flush_instruction_cache)
    -#if defined(CONFIG_8xx)
    - isync
    - lis r5, IDC_INVALL@h
    - mtspr SPRN_IC_CST, r5
    -#elif defined(CONFIG_4xx)
    +#if defined(CONFIG_4xx)
    #ifdef CONFIG_403GCX
    li r3, 512
    mtctr r3
    @@ -334,9 +331,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
    mfspr r3,SPRN_HID0
    ori r3,r3,HID0_ICFI
    mtspr SPRN_HID0,r3
    -#endif /* CONFIG_8xx/4xx */
    +#endif /* CONFIG_4xx */
    isync
    blr
    +#endif /* CONFIG_PPC_8xx */

    /*
    * Write any modified data cache blocks out to memory
    diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
    index b75c461..e2ce480 100644
    --- a/arch/powerpc/mm/8xx_mmu.c
    +++ b/arch/powerpc/mm/8xx_mmu.c
    @@ -181,3 +181,10 @@ void set_context(unsigned long id, pgd_t *pgd)
    /* sync */
    mb();
    }
    +
    +void flush_instruction_cache(void)
    +{
    + isync();
    + mtspr(SPRN_IC_CST, IDC_INVALL);
    + isync();
    +}
    --
    2.1.0
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