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    Subject[tip:x86/microcode] x86/microcode/intel: Use *wrmsrl variants
    Commit-ID:  c416e6117575213a5a962149620684a09f9e4ece
    Gitweb: http://git.kernel.org/tip/c416e6117575213a5a962149620684a09f9e4ece
    Author: Borislav Petkov <bp@suse.de>
    AuthorDate: Wed, 3 Feb 2016 12:33:40 +0100
    Committer: Ingo Molnar <mingo@kernel.org>
    CommitDate: Tue, 9 Feb 2016 11:41:17 +0100

    x86/microcode/intel: Use *wrmsrl variants

    ... and drop the 32-bit casting games which we had to do at the time
    because wrmsr() was unforgiving then, see c3fd0bd5e19a from the
    full history tree:

    commit c3fd0bd5e19aaff9cdd104edff136a2023db657e
    Author: Linus Torvalds <torvalds@home.osdl.org>
    Date: Tue Feb 17 23:23:41 2004 -0800

    Fix up the microcode update on regular 32-bit x86. Our wrmsr()
    is a bit unforgiving and really doesn't like 64-bit values.
    ...

    Tested-by: Thomas Voegtle <tv@lio96.de>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Link: http://lkml.kernel.org/r/1454499225-21544-13-git-send-email-bp@alien8.de
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    ---
    arch/x86/kernel/cpu/microcode/intel.c | 14 +++++---------
    1 file changed, 5 insertions(+), 9 deletions(-)

    diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
    index 35186a0..ff0b449 100644
    --- a/arch/x86/kernel/cpu/microcode/intel.c
    +++ b/arch/x86/kernel/cpu/microcode/intel.c
    @@ -370,7 +370,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci)
    native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
    csig.pf = 1 << ((val[1] >> 18) & 7);
    }
    - native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
    + native_wrmsrl(MSR_IA32_UCODE_REV, 0);

    /* As documented in the SDM: Do a CPUID 1 here */
    sync_core();
    @@ -648,10 +648,8 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
    return 0;

    /* write microcode via MSR 0x79 */
    - native_wrmsr(MSR_IA32_UCODE_WRITE,
    - (unsigned long)mc->bits,
    - (unsigned long)mc->bits >> 16 >> 16);
    - native_wrmsr(MSR_IA32_UCODE_REV, 0, 0);
    + native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
    + native_wrmsrl(MSR_IA32_UCODE_REV, 0);

    /* As documented in the SDM: Do a CPUID 1 here */
    sync_core();
    @@ -860,10 +858,8 @@ static int apply_microcode_intel(int cpu)
    return 0;

    /* write microcode via MSR 0x79 */
    - wrmsr(MSR_IA32_UCODE_WRITE,
    - (unsigned long) mc->bits,
    - (unsigned long) mc->bits >> 16 >> 16);
    - wrmsr(MSR_IA32_UCODE_REV, 0, 0);
    + wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
    + wrmsrl(MSR_IA32_UCODE_REV, 0);

    /* As documented in the SDM: Do a CPUID 1 here */
    sync_core();
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