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SubjectRe: [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding
On Wed, Feb 24, 2016 at 12:26:44PM -0600, Aravind Gopalakrishnan wrote:
> Hmm, we call this from mce_threshold_block_init() with set_lvt_off = 1 to
> write LVT offset value to MCi_MISC.
> And we call this from store_interrupt_enable() to program APIC INT TYPE-
> if (tr->b->interrupt_enable)
> hi |= INT_TYPE_APIC;
>
> and from store_threshold_limit() to re-set the "error count"-
> hi = (hi & ~MASK_ERR_COUNT_HI) |
> (new_count & THRESHOLD_MAX);
>
> So I thought it fit the description as to "what" it does..

threshold_restart_bank() reprograms the MISC MSR after sanity-checking
the fields supplied for that MSR. store_threshold_limit() sets the error
count, store_interrupt_enable() enables/disables the interrupt and both
call threshold_restart_bank() to do that.

But this is basically spelling the code now - I don't think we need to
comment in that detail.

/*
* Called via smp_call_function_single(), must be called with correct
* cpu affinity.
*/

is also useless.

> "This function provides user with capabilities to re-program the
> 'thresold_limit' and 'interrupt_enable' sysfs attributes"

No sorry, I don't want to be explaining every line. Just say: "Reprogram
the MISC MSR behind this threshold bank."

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.

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