Messages in this thread Patch in this message | | | Subject | Re: [PATCH 4/4] x86/mce/AMD: Add comments for easier understanding | From | Aravind Gopalakrishnan <> | Date | Wed, 24 Feb 2016 12:26:44 -0600 |
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On 2/23/2016 6:35 AM, Borislav Petkov wrote: > On Tue, Feb 16, 2016 at 03:45:11PM -0600, Aravind Gopalakrishnan wrote: >> >> /* >> + * Set the error_count and interrupt_enable sysfs attributes here. >> + * This function gets called during the init phase and when someone >> + * makes changes to either of the sysfs attributes. >> + * During init phase, we also program Interrupt type as 'APIC' and >> + * verify if LVT offset obtained from MCx_MISC is valid. >> * Called via smp_call_function_single(), must be called with correct >> * cpu affinity. >> */ > I don't think that's what threshold_restart_bank() does...
Hmm, we call this from mce_threshold_block_init() with set_lvt_off = 1 to write LVT offset value to MCi_MISC. And we call this from store_interrupt_enable() to program APIC INT TYPE- if (tr->b->interrupt_enable) hi |= INT_TYPE_APIC;
and from store_threshold_limit() to re-set the "error count"- hi = (hi & ~MASK_ERR_COUNT_HI) | (new_count & THRESHOLD_MAX);
So I thought it fit the description as to "what" it does..
> Also, that comment is too much - it shouldn't explain "what" but "why".
How about-
"This function provides user with capabilities to re-program the 'thresold_limit' and 'interrupt_enable' sysfs attributes"
>> @@ -262,6 +267,11 @@ static int setup_APIC_deferred_error(int reserved, int new) >> return reserved; >> } >> >> +/* >> + * Obtain LVT offset from MSR_CU_DEF_ERR and call >> + * setup_APIC_deferred_error() to program relevant APIC register. >> + * Also, register a deferred error interrupt handler >> + */ > No, that's basically spelling what the code does.
Ok, I'll remove this.
>> static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) >> { >> u32 low = 0, high = 0; >> @@ -338,6 +348,14 @@ nextaddr_out: >> return addr; >> } >> >> +/* >> + * struct threshold_block descriptor tracks useful info regarding the >> + * banks' MISC register. Among other things, it tracks whether interrupt >> + * is possible for the given bank, the threshold limit and the sysfs object >> + * that outputs these info. > That should be in form of comments explaining what the members of struct > threshold_block are, where that struct is defined.
Ok, I'll remove comments here and add it to arch/x86/include/asm/amd_nb.h
>> Initializing the struct here, programming >> + * LVT offset for threshold interrupts and registering a interrupt handler >> + * if we haven't already done so > Also spelling the code.
Will remove this
Thanks, -Aravind.
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