Messages in this thread Patch in this message | | | From | Paul Burton <> | Subject | [PATCH 02/15] MIPS: traps: Make sure secondary cores have a sane ebase register | Date | Wed, 3 Feb 2016 03:15:22 +0000 |
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From: Markos Chandras <markos.chandras@imgtec.com>
We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> ---
arch/mips/kernel/traps.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index bafcb7a..1fb5f8a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2125,6 +2125,13 @@ void per_cpu_trap_init(bool is_boot_cpu) * o read IntCtl.IPFDC to determine the fast debug channel interrupt */ if (cpu_has_mips_r2_r6) { + /* + * We shouldn't trust a secondary core has a sane EBASE register + * so use the one calculated by the boot CPU. + */ + if (!is_boot_cpu) + write_c0_ebase(ebase); + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; -- 2.7.0
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