Messages in this thread | | | Date | Sun, 14 Feb 2016 09:03:06 +0100 | From | Lars Persson <> | Subject | Re: [PATCH 1/2] clk: add device tree binding for artpec-6 pll1 clock |
| |
On 02/12/2016 05:39 PM, Rob Herring wrote: > On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote: >> Add device tree documentation for the main PLL in the Artpec-6 SoC. > Roughly how many clocks does this SoC have? It will have 17 clocks declared in the device tree and three SoC-specific clock drivers.
> >> Signed-off-by: Lars Persson <larper@axis.com> >> --- >> Documentation/devicetree/bindings/clock/artpec6.txt | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt >> new file mode 100644 >> index 0000000..521fec8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/artpec6.txt >> @@ -0,0 +1,16 @@ >> +* Clock bindings for Axis ARTPEC-6 chip >> + >> +Required properties: >> +- #clock-cells: Should be <0> >> +- compatible: Should be "axis,artpec6-pll1-clock" >> +- reg: Address and length of the DEVSTAT register. >> +- clocks: The PLL's input clock. >> + >> +Examples: >> + >> +pll1_clk: pll1_clk { >> + #clock-cells = <0>; >> + compatible = "axis,artpec6-pll1-clock"; >> + reg = <0xf8000000 4>; >> + clocks = <&ext_clk>; >> +}; >> -- >> 2.1.4 >>
| |