Messages in this thread | | | Date | Fri, 9 Dec 2016 17:33:28 +0100 | From | Borislav Petkov <> | Subject | Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support |
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On Fri, Dec 09, 2016 at 06:32:33PM +0300, Kirill A. Shutemov wrote: > Something like this? > > diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c > index 6687ab953257..366aad972025 100644 > --- a/arch/x86/boot/cpuflags.c > +++ b/arch/x86/boot/cpuflags.c > @@ -70,16 +70,22 @@ int has_eflag(unsigned long mask) > # define EBX_REG "=b" > #endif > > -static inline void cpuid(u32 id, u32 *a, u32 *b, u32 *c, u32 *d) > +static inline void cpuid_count(u32 id, u32 count, > + u32 *a, u32 *b, u32 *c, u32 *d) > { > + *a = id; > + *c = count; > + > asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif \n\t" > "cpuid \n\t" > ".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif \n\t" > : "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b) > - : "a" (id) > + : "a" (id), "c" (count) > ); > } > > +#define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
LGTM.
Thanks.
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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