Messages in this thread Patch in this message | | | Date | Mon, 5 Dec 2016 11:25:09 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH] perf/x86: fix event counter update issue |
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On Fri, Dec 02, 2016 at 12:58:17PM +0000, Odzioba, Lukasz wrote: > On Tuesday, November 29, 2016 9:33 PM, Liang, Kan wrote: > > Yes, the patch as below fixes the issue on my SLM. > > It works for me as well. > Can we still have it in 4.9?
I'll certainly, try. I've queued it as per the below.
--- Subject: perf,x86: Fix full width counter, counter overflow Date: Tue, 29 Nov 2016 20:33:28 +0000
Lukasz reported that perf stat counters overflow is broken on KNL/SLM.
Both these parts have full_width_write set, and that does indeed have a problem. In order to deal with counter wrap, we must sample the counter at at least half the counter period (see also the sampling theorem) such that we can unambiguously reconstruct the count.
However commit:
069e0c3c4058 ("perf/x86/intel: Support full width counting")
sets the sampling interval to the full period, not half.
Fixing that exposes another issue, in that we must not sign extend the delta value when we shift it right; the counter cannot have decremented after all.
With both these issues fixed, counter overflow functions correctly again.
Cc: "mingo@redhat.com" <mingo@redhat.com> Cc: "ak@linux.intel.com" <ak@linux.intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Reported-by: Lukasz Odzioba <lukasz.odzioba@intel.com> Tested-by: "Liang, Kan" <kan.liang@intel.com> Tested-by: "Odzioba, Lukasz" <lukasz.odzioba@intel.com> Fixes: 069e0c3c4058 ("perf/x86/intel: Support full width counting") Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> --- arch/x86/events/core.c | 2 +- arch/x86/events/intel/core.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
--- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -69,7 +69,7 @@ u64 x86_perf_event_update(struct perf_ev int shift = 64 - x86_pmu.cntval_bits; u64 prev_raw_count, new_raw_count; int idx = hwc->idx; - s64 delta; + u64 delta; if (idx == INTEL_PMC_IDX_FIXED_BTS) return 0; --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) /* Support full width counters using alternative MSR range */ if (x86_pmu.intel_cap.full_width_write) { - x86_pmu.max_period = x86_pmu.cntval_mask; + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; x86_pmu.perfctr = MSR_IA32_PMC0; pr_cont("full-width counters, "); }
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