Messages in this thread | | | Date | Tue, 29 Nov 2016 20:34:12 -0500 (EST) | Subject | Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly | From | David Miller <> |
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From: Zumeng Chen <zumeng.chen@windriver.com> Date: Mon, 28 Nov 2016 21:55:00 +0800
> When a hardware issue happened as described by inline comments, the register > write pattern looks like the following: > > <write ~MACB_BIT(RE)> > + wmb(); > <write MACB_BIT(RE)> > > There might be a memory barrier between these two write operations, so add wmb > to ensure an flip from 0 to 1 for NCR. > > Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com> > --- > > V2 changes: > > Add the same wmb for at91ether as well based on reviewer's suggestion.
Applied, thanks.
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