Messages in this thread | | | Date | Wed, 16 Nov 2016 21:45:18 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH v2] x86/cpufeatures: Enable new AVX512 cpu features |
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On Wed, Nov 16, 2016 at 12:11:00PM -0800, Gayatri Kammela wrote: > Add a few new AVX512 instruction groups/features for enumeration in > /proc/cpuinfo: AVX512IFMA and AVX512VBMI. > > Clear the flags in fpu_xstate_clear_all_cpu_caps(). > > CPUID.(EAX=7,ECX=0):EBX[bit 21] AVX512IFMA > CPUID.(EAX=7,ECX=0):ECX[bit 1] AVX512VBMI > > Detailed information of cpuid bits for the features can be found at > https://bugzilla.kernel.org/show_bug.cgi?id=187891 > > Cc: Borislav Petkov <bp@alien8.de> > Cc: H. Peter Anvin <hpa@linux.intel.com> > Cc: Ravi Shankar <ravi.v.shankar@intel.com> > Cc: Fenghua Yu <fenghua.yu@intel.com> > Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> > --- > > v1: Change commit message to add stable reference source. > > arch/x86/include/asm/cpufeatures.h | 2 ++ > arch/x86/kernel/fpu/xstate.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 4a413485f9eb..c722fcc18a15 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -225,6 +225,7 @@ > #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ > #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ > #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ > +#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */ > #define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ > #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ > #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ > @@ -279,6 +280,7 @@ > #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ > +#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > > diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c > index 4ea2a59483c7..92411568e320 100644 > --- a/arch/x86/kernel/fpu/xstate.c > +++ b/arch/x86/kernel/fpu/xstate.c > @@ -56,6 +56,7 @@ void fpu__xstate_clear_all_cpu_caps(void) > setup_clear_cpu_cap(X86_FEATURE_AVX); > setup_clear_cpu_cap(X86_FEATURE_AVX2); > setup_clear_cpu_cap(X86_FEATURE_AVX512F); > + setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA); > setup_clear_cpu_cap(X86_FEATURE_AVX512PF); > setup_clear_cpu_cap(X86_FEATURE_AVX512ER); > setup_clear_cpu_cap(X86_FEATURE_AVX512CD); > @@ -64,6 +65,7 @@ void fpu__xstate_clear_all_cpu_caps(void) > setup_clear_cpu_cap(X86_FEATURE_AVX512VL); > setup_clear_cpu_cap(X86_FEATURE_MPX); > setup_clear_cpu_cap(X86_FEATURE_XGETBV1); > + setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI); > setup_clear_cpu_cap(X86_FEATURE_PKU);
Nice!
Reviewed-by: Borislav Petkov <bp@suse.de>
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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