Messages in this thread | | | Date | Thu, 10 Nov 2016 09:00:13 +0100 | From | Ingo Molnar <> | Subject | Re: [PATCH] perf/x86: Fix overlap counter scheduling bug |
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* Peter Zijlstra <peterz@infradead.org> wrote:
> On Wed, Nov 09, 2016 at 03:25:15PM +0100, Robert Richter wrote: > > On 08.11.16 19:27:39, Peter Zijlstra wrote: > > > The comment with EVENT_CONSTRAINT_OVERLAP states: "This is the case if > > > the counter mask of such an event is not a subset of any other counter > > > mask of a constraint with an equal or higher weight". > > > > > > Esp. that latter part is of interest here I think, our overlapping mask > > > is 0x0e, that has 3 bits set and is the highest weight mask in on the > > > PMU, therefore it will be placed last. Can we still create a scenario > > > where we would need to rewind that? > > > > > > The scenario for AMD Fam15h is we're having masks like: > > > > > > 0x3F -- 111111 > > > 0x38 -- 111000 > > > 0x07 -- 000111 > > > > > > 0x09 -- 001001 > > > > > > And we mark 0x09 as overlapping, because it is not a direct subset of > > > 0x38 or 0x07 and has less weight than either of those. This means we'll > > > first try and place the 0x09 event, then try and place 0x38/0x07 events. > > > Now imagine we have: > > > > > > 3 * 0x07 + 0x09 > > > > > > and the initial pick for the 0x09 event is counter 0, then we'll fail to > > > place all 0x07 events. So we'll pop back, try counter 4 for the 0x09 > > > event, and then re-try all 0x07 events, which will now work. > > > > > > > > > > > > But given, that in the uncore case, the overlapping event is the > > > heaviest mask, I don't think this can happen. Or did I overlook > > > something.... takes a bit to page all this back in. > > > > Right, IMO 0xE mask may not be marked as overlapping. It is placed > > last and if there is no space left we are lost. There is no other > > combination or state we could try then. So the fix is to remove the > > overlapping bit for that counter, the state is then never saved. > > > > This assumes there are no other counters than 0x3 and 0xc that overlap > > with 0xe. It becomes a bit tricky if there is another counter with the > > same or higher weight that overlaps with 0xe, e.g. 0x7. > > As per a prior mail, the masks on the PMU in question are: > > 0x01 - 0001 > 0x03 - 0011 > 0x0e - 1110 > 0x0c - 1100 > > But since all the masks that have overlap (0xe -> {0xc,0x3}) and (0x3 -> > 0x1) are of heavier weight, it should all work out I think. > > So yes, something like the below (removing the OVERLAP bit) looks like > its sufficient.
Would it be possible to also add debug code (or some other mechanism) to disallow such buggy EVENT_CONSTRAINT_OVERLAP() definitions?
Thanks,
Ingo
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