lkml.org 
[lkml]   [2016]   [Oct]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot
On Thu, 27 Oct 2016, Andrejczuk, Grzegorz wrote:
> > > init_intel_energy_perf(c);
> > > +
> > > + /*
> > > + * Setting ring 3 MONITOR/MWAIT for thread
> > > + * when CPU is Xeon Phi Family x200 (KnightsLanding).
> > > + */
> > > + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)
> >
> > Please move this conditional into the probe function.
> >
> > > + probe_xeon_phi_r3mwait(c);
> >
> > Can you please check with your hardware people, whether this function
> > is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID
> > fault enable) is detectable via the PLATFORM_INFO MSR. I would be
> > surprised if this thing is not detectable in some way.
> >
> > I really prefer detectable things over hardcoded crap which depends on
> > model information.
>
> I asked hardware people and MSR 0x140 should be called
> MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating
> that this bit can be set. Unfortunately hardcoded crap has to be used.

Can you please tell your hardware folks, that non discoverable features are
a horror? We really need unique detection of features across all the
various cpu platforms. Making stuff depend on models, stepping results in a
nightmare.

Thanks,

tglx

\
 
 \ /
  Last update: 2016-10-27 20:25    [W:1.813 / U:0.056 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site