On Wed, Oct 26, 2016 at 11:39:47PM +0200, Thomas Gleixner wrote:
> On Sat, 22 Oct 2016, Fenghua Yu wrote:
> > This version should cover all comments from Thomas.
> 
> Emphasis on should :)
> 
> But this series is a major step forward and I decided to merge the first
> lot:
> 
> > 0001-Documentation-ABI-Add-a-document-entry-for-cache-id.patch
> > 0002-cacheinfo-Introduce-cache-id.patch
> > 0003-x86-intel_cacheinfo-Enable-cache-id-in-x86.patch
> > 0004-x86-intel_rdt-Feature-discovery.patch
> 
> > 0006-x86-intel_rdt-Add-CONFIG-Makefile-and-basic-initiali.patch
> > 0007-x86-intel_rdt-Add-Haswell-feature-discovery.patch
> > 0008-x86-intel_rdt-Pick-up-L3-L2-RDT-parameters-from-CPUID.patch
> > 0009-x86-cqm-Move-PQR_ASSOC-management-code-into-generic-.patch
> 
> I fixed up #0004 (including Borislavs comments) and polished some of the
> changelogs a bit.
> 
> This reduces the size of the series and prevents that these parts get
> [un]intentionally fat fingered once again.
> 
> I intentionally left out the documentation patch as that one needs to be
> updated when you address the max closid issues.
> 
> Please work against tip x86/cache from now on.
> 
> The remaining issues are not that big, so I think we are really close.
> 
> Thanks
> 
>        tglx

This is really great!

I'm working on releasing updated remaining patches based on the tip x86/cache.

Thank you, Thomas!

-Fenghua