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SubjectRe: [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery
On Fri, 14 Oct 2016, Fenghua Yu wrote:
> +static inline bool cache_alloc_hsw_probe(void)
> +{
> + u32 l, h;
> + u32 max_cbm = BIT_MASK(20) - 1;

Two options here:

+ u32 l, h, max_cbm = BIT_MASK(20) - 1;

or

+ u32 max_cbm = BIT_MASK(20) - 1;
+ u32 l, h;

I personally prefer #1, but I can accept #2 as well. Both are quick to
parse while the one you chose is stopping the reading flow.

> +
> + if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
> + return false;
> + rdmsr(IA32_L3_CBM_BASE, l, h);
> + if (l != max_cbm)
> + return false;
> +
> + return true;

return l == max_cbm;

Hmm?

> +}
> +
> static inline bool get_rdt_resources(void)
> {
> bool ret = false;
>
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> + boot_cpu_data.x86 == 6 &&
> + boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X)
> + return cache_alloc_hsw_probe();

Can you please stick that model check into the probe function and do:

if (cache_alloc_hsw_probe())
return true;
> +
> if (!boot_cpu_has(X86_FEATURE_RDT_A))
> return false;
> if (boot_cpu_has(X86_FEATURE_CAT_L3))

Thanks,

tglx

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