| From | Kamal Mostafa <> | Subject | [PATCH 4.2.y-ckt 196/268] clk: xgene: Fix divider with non-zero shift value | Date | Wed, 27 Jan 2016 12:34:17 -0800 |
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4.2.8-ckt3 -stable review patch. If anyone has any objections, please let me know.
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From: Loc Ho <lho@apm.com>
commit 1382ea631ddddb634850a3795527db0feeff5aaf upstream.
The X-Gene clock driver missed the divider shift operation when set the divider value.
Signed-off-by: Loc Ho <lho@apm.com> Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kamal Mostafa <kamal@canonical.com> --- drivers/clk/clk-xgene.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index f26b3ac..2f9668b 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -353,7 +353,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, /* Set new divider */ data = xgene_clk_read(pclk->param.divider_reg + pclk->param.reg_divider_offset); - data &= ~((1 << pclk->param.reg_divider_width) - 1); + data &= ~((1 << pclk->param.reg_divider_width) - 1) + << pclk->param.reg_divider_shift; data |= divider; xgene_clk_write(data, pclk->param.divider_reg + pclk->param.reg_divider_offset); -- 1.9.1
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