Messages in this thread | | | Subject | Re: futex atomic vs ordering constraints | From | Chris Metcalf <> | Date | Fri, 4 Sep 2015 13:25:55 -0400 |
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On 09/02/2015 05:18 PM, Linus Torvalds wrote: > For example, on x86, the locked instructions are obviously already > sufficiently strong, but even if they weren't, kernel entry/exit is > documented to be a serializing instruction (which is something > insanely much stronger than just memory ordering). And I suspect there > are similar issues on a lot of architectures where the memory ordering > is done by the core, but the cache subsystem is strongly ordered (ie > saen good SMP systems - so it sounds like tile needs the smp_mb()'s, > but I would almost suspect that POWER and ARM might *not* need them).
Because POWER and ARM have serializing kernel entry/exit? I think tile has relatively conventional cache/memory semantics, but it's certainly true there is implicit memory ordering guarantee for kernel entry/exit.
-- Chris Metcalf, EZChip Semiconductor http://www.ezchip.com
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