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SubjectRE: [Patch V0] x86, mce: Don't clear global error reporting banks during cpu_offline
> What does that mean? What does SGX have to do with MCI_CTL registers?
> Explain that in the commit message so that !Intel people can understand.

I think the SGX folk are worried that it might be possible to compromise the
integrity of code running in SGX if an attacker has control of the host and can
inject errors which are ignored because of MCi_CTL settings. Hence they have
the h/w drop out of SGX if they see anyone tamper with MCi_CTL

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