lkml.org 
[lkml]   [2015]   [Sep]   [20]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH v3 1/2] mfd: arizona: Add register bits to support the ANC block
On Wed, 09 Sep 2015, Charles Keepax wrote:

> Some Arizona devices have a hardware ANC block present. This patch adds
> the registers necessary to configure this hardware block.
>
> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
> ---
>
> Changes since v2:
> - Added missing default for 0xF0A
>
> Thanks,
> Charles
>
> drivers/mfd/wm5110-tables.c | 186 +++++++++++++++++++++++++++++++++
> include/linux/mfd/arizona/registers.h | 70 ++++++++++++
> 2 files changed, 256 insertions(+), 0 deletions(-)

Applied, thanks.

> diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
> index dae04dd..f154991 100644
> --- a/drivers/mfd/wm5110-tables.c
> +++ b/drivers/mfd/wm5110-tables.c
> @@ -1637,6 +1637,185 @@ static const struct reg_default wm5110_reg_default[] = {
> { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
> { 0x00000F00, 0x0000 }, /* R3840 - Clock Control */
> { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */
> + { 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */
> + { 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */
> + { 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */
> + { 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */
> + { 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */
> + { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */
> + { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */
> + { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */
> + { 0x00000F10, 0x0000 }, /* R3856 - ANC Coefficient */
> + { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */
> + { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */
> + { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */
> + { 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */
> + { 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */
> + { 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */
> + { 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */
> + { 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */
> + { 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */
> + { 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */
> + { 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */
> + { 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */
> + { 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */
> + { 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */
> + { 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */
> + { 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */
> + { 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */
> + { 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */
> + { 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */
> + { 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */
> + { 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */
> + { 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */
> + { 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */
> + { 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */
> + { 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */
> + { 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */
> + { 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */
> + { 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */
> + { 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */
> + { 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */
> + { 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */
> + { 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */
> + { 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */
> + { 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */
> + { 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */
> + { 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */
> + { 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */
> + { 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */
> + { 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */
> + { 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */
> + { 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */
> + { 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */
> + { 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */
> + { 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */
> + { 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */
> + { 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */
> + { 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */
> + { 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */
> + { 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */
> + { 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */
> + { 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */
> + { 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */
> + { 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */
> + { 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */
> + { 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */
> + { 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */
> + { 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */
> + { 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */
> + { 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */
> + { 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */
> + { 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */
> + { 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */
> + { 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */
> + { 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */
> + { 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */
> + { 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */
> + { 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */
> + { 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */
> + { 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */
> + { 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */
> + { 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */
> + { 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */
> + { 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */
> + { 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */
> + { 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */
> + { 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */
> + { 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */
> + { 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */
> + { 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */
> + { 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */
> + { 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */
> + { 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */
> + { 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */
> + { 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */
> + { 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */
> + { 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */
> + { 0x00000F70, 0x0000 }, /* R3952 - FCR Filter Control */
> + { 0x00000F72, 0x0004 }, /* R3954 - FCR ADC Reformatter Control */
> + { 0x00000F73, 0x0004 }, /* R3955 - ANC Coefficient */
> + { 0x00000F74, 0x0002 }, /* R3956 - ANC Coefficient */
> + { 0x00000F75, 0x0000 }, /* R3957 - ANC Coefficient */
> + { 0x00000F76, 0x0010 }, /* R3958 - ANC Coefficient */
> + { 0x00000F77, 0x0000 }, /* R3959 - ANC Coefficient */
> + { 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */
> + { 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */
> + { 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */
> + { 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */
> + { 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */
> + { 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */
> + { 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */
> + { 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */
> + { 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */
> + { 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */
> + { 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */
> + { 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */
> + { 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */
> + { 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */
> + { 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */
> + { 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */
> + { 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */
> + { 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */
> + { 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */
> + { 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */
> + { 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */
> + { 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */
> + { 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */
> + { 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */
> + { 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */
> + { 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */
> + { 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */
> + { 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */
> + { 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */
> + { 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */
> + { 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */
> + { 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */
> + { 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */
> + { 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */
> + { 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */
> + { 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */
> + { 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */
> + { 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */
> + { 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */
> + { 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */
> + { 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */
> + { 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */
> + { 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */
> + { 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */
> + { 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */
> + { 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */
> + { 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */
> + { 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */
> + { 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */
> + { 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */
> + { 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */
> + { 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */
> + { 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */
> + { 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */
> + { 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */
> + { 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */
> + { 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */
> + { 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */
> + { 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */
> + { 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */
> + { 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */
> + { 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */
> + { 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */
> + { 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */
> + { 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */
> + { 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */
> + { 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */
> + { 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */
> + { 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */
> + { 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */
> + { 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */
> + { 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */
> + { 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */
> + { 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */
> + { 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */
> + { 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */
> + { 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */
> { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
> { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */
> { 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */
> @@ -2716,6 +2895,13 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
> case ARIZONA_CLOCK_CONTROL:
> case ARIZONA_ANC_SRC:
> case ARIZONA_DSP_STATUS:
> + case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END:
> + case ARIZONA_FCL_FILTER_CONTROL:
> + case ARIZONA_FCL_ADC_REFORMATTER_CONTROL:
> + case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END:
> + case ARIZONA_FCR_FILTER_CONTROL:
> + case ARIZONA_FCR_ADC_REFORMATTER_CONTROL:
> + case ARIZONA_FCR_COEFF_START ... ARIZONA_FCR_COEFF_END:
> case ARIZONA_DSP1_CONTROL_1:
> case ARIZONA_DSP1_CLOCKING_1:
> case ARIZONA_DSP1_STATUS_1:
> diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
> index 11affb3..fdb12bf 100644
> --- a/include/linux/mfd/arizona/registers.h
> +++ b/include/linux/mfd/arizona/registers.h
> @@ -1050,6 +1050,16 @@
> #define ARIZONA_CLOCK_CONTROL 0xF00
> #define ARIZONA_ANC_SRC 0xF01
> #define ARIZONA_DSP_STATUS 0xF02
> +#define ARIZONA_ANC_COEFF_START 0xF08
> +#define ARIZONA_ANC_COEFF_END 0xF12
> +#define ARIZONA_FCL_FILTER_CONTROL 0xF15
> +#define ARIZONA_FCL_ADC_REFORMATTER_CONTROL 0xF17
> +#define ARIZONA_FCL_COEFF_START 0xF18
> +#define ARIZONA_FCL_COEFF_END 0xF69
> +#define ARIZONA_FCR_FILTER_CONTROL 0xF70
> +#define ARIZONA_FCR_ADC_REFORMATTER_CONTROL 0xF72
> +#define ARIZONA_FCR_COEFF_START 0xF73
> +#define ARIZONA_FCR_COEFF_END 0xFC4
> #define ARIZONA_DSP1_CONTROL_1 0x1100
> #define ARIZONA_DSP1_CLOCKING_1 0x1101
> #define ARIZONA_DSP1_STATUS_1 0x1104
> @@ -7823,6 +7833,66 @@
> #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */
>
> /*
> + * R3840 (0xF00) - Clock Control
> + */
> +#define ARIZONA_EXT_NG_SEL_CLR 0x0080 /* EXT_NG_SEL_CLR */
> +#define ARIZONA_EXT_NG_SEL_CLR_MASK 0x0080 /* EXT_NG_SEL_CLR */
> +#define ARIZONA_EXT_NG_SEL_CLR_SHIFT 7 /* EXT_NG_SEL_CLR */
> +#define ARIZONA_EXT_NG_SEL_CLR_WIDTH 1 /* EXT_NG_SEL_CLR */
> +#define ARIZONA_EXT_NG_SEL_SET 0x0040 /* EXT_NG_SEL_SET */
> +#define ARIZONA_EXT_NG_SEL_SET_MASK 0x0040 /* EXT_NG_SEL_SET */
> +#define ARIZONA_EXT_NG_SEL_SET_SHIFT 6 /* EXT_NG_SEL_SET */
> +#define ARIZONA_EXT_NG_SEL_SET_WIDTH 1 /* EXT_NG_SEL_SET */
> +#define ARIZONA_CLK_R_ENA_CLR 0x0020 /* CLK_R_ENA_CLR */
> +#define ARIZONA_CLK_R_ENA_CLR_MASK 0x0020 /* CLK_R_ENA_CLR */
> +#define ARIZONA_CLK_R_ENA_CLR_SHIFT 5 /* CLK_R_ENA_CLR */
> +#define ARIZONA_CLK_R_ENA_CLR_WIDTH 1 /* CLK_R_ENA_CLR */
> +#define ARIZONA_CLK_R_ENA_SET 0x0010 /* CLK_R_ENA_SET */
> +#define ARIZONA_CLK_R_ENA_SET_MASK 0x0010 /* CLK_R_ENA_SET */
> +#define ARIZONA_CLK_R_ENA_SET_SHIFT 4 /* CLK_R_ENA_SET */
> +#define ARIZONA_CLK_R_ENA_SET_WIDTH 1 /* CLK_R_ENA_SET */
> +#define ARIZONA_CLK_NG_ENA_CLR 0x0008 /* CLK_NG_ENA_CLR */
> +#define ARIZONA_CLK_NG_ENA_CLR_MASK 0x0008 /* CLK_NG_ENA_CLR */
> +#define ARIZONA_CLK_NG_ENA_CLR_SHIFT 3 /* CLK_NG_ENA_CLR */
> +#define ARIZONA_CLK_NG_ENA_CLR_WIDTH 1 /* CLK_NG_ENA_CLR */
> +#define ARIZONA_CLK_NG_ENA_SET 0x0004 /* CLK_NG_ENA_SET */
> +#define ARIZONA_CLK_NG_ENA_SET_MASK 0x0004 /* CLK_NG_ENA_SET */
> +#define ARIZONA_CLK_NG_ENA_SET_SHIFT 2 /* CLK_NG_ENA_SET */
> +#define ARIZONA_CLK_NG_ENA_SET_WIDTH 1 /* CLK_NG_ENA_SET */
> +#define ARIZONA_CLK_L_ENA_CLR 0x0002 /* CLK_L_ENA_CLR */
> +#define ARIZONA_CLK_L_ENA_CLR_MASK 0x0002 /* CLK_L_ENA_CLR */
> +#define ARIZONA_CLK_L_ENA_CLR_SHIFT 1 /* CLK_L_ENA_CLR */
> +#define ARIZONA_CLK_L_ENA_CLR_WIDTH 1 /* CLK_L_ENA_CLR */
> +#define ARIZONA_CLK_L_ENA_SET 0x0001 /* CLK_L_ENA_SET */
> +#define ARIZONA_CLK_L_ENA_SET_MASK 0x0001 /* CLK_L_ENA_SET */
> +#define ARIZONA_CLK_L_ENA_SET_SHIFT 0 /* CLK_L_ENA_SET */
> +#define ARIZONA_CLK_L_ENA_SET_WIDTH 1 /* CLK_L_ENA_SET */
> +
> +/*
> + * R3841 (0xF01) - ANC SRC
> + */
> +#define ARIZONA_IN_RXANCR_SEL_MASK 0x0070 /* IN_RXANCR_SEL - [4:6] */
> +#define ARIZONA_IN_RXANCR_SEL_SHIFT 4 /* IN_RXANCR_SEL - [4:6] */
> +#define ARIZONA_IN_RXANCR_SEL_WIDTH 3 /* IN_RXANCR_SEL - [4:6] */
> +#define ARIZONA_IN_RXANCL_SEL_MASK 0x0007 /* IN_RXANCL_SEL - [0:2] */
> +#define ARIZONA_IN_RXANCL_SEL_SHIFT 0 /* IN_RXANCL_SEL - [0:2] */
> +#define ARIZONA_IN_RXANCL_SEL_WIDTH 3 /* IN_RXANCL_SEL - [0:2] */
> +
> +/*
> + * R3863 (0xF17) - FCL ADC Reformatter Control
> + */
> +#define ARIZONA_FCL_MIC_MODE_SEL 0x000C /* FCL_MIC_MODE_SEL - [2:3] */
> +#define ARIZONA_FCL_MIC_MODE_SEL_SHIFT 2 /* FCL_MIC_MODE_SEL - [2:3] */
> +#define ARIZONA_FCL_MIC_MODE_SEL_WIDTH 2 /* FCL_MIC_MODE_SEL - [2:3] */
> +
> +/*
> + * R3954 (0xF72) - FCR ADC Reformatter Control
> + */
> +#define ARIZONA_FCR_MIC_MODE_SEL 0x000C /* FCR_MIC_MODE_SEL - [2:3] */
> +#define ARIZONA_FCR_MIC_MODE_SEL_SHIFT 2 /* FCR_MIC_MODE_SEL - [2:3] */
> +#define ARIZONA_FCR_MIC_MODE_SEL_WIDTH 2 /* FCR_MIC_MODE_SEL - [2:3] */
> +
> +/*
> * R4352 (0x1100) - DSP1 Control 1
> */
> #define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */

--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


\
 
 \ /
  Last update: 2015-09-20 06:41    [W:0.052 / U:3.964 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site