Messages in this thread | | | Date | Tue, 4 Aug 2015 13:41:15 -0700 (PDT) | From | Vikas Shivappa <> | Subject | Re: [PATCH 3/9] x86/intel_rdt: Cache Allocation documentation and cgroup usage guide |
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On Tue, 28 Jul 2015, Peter Zijlstra wrote:
> On Wed, Jul 01, 2015 at 03:21:04PM -0700, Vikas Shivappa wrote: > > Please edit this document to have consistent spacing. Its really hard to > read this. Every time I spot a misplaced space my brain stumbles and I > need to restart.
Will fix all the spacing and other indentions issues mentioned. Thanks for pointing them all out. Although the other documents I see dont have a consistent format completely which is what confused me, this format would be better.
>> + >> +The following considerations are done for the PQR MSR write so that it >> +has minimal impact on scheduling hot path: >> +- This path doesnt exist on any non-intel platforms. > > !x86 I think you mean, its entirely possible to have the code present > on AMD systems for instance. > >> +- On Intel platforms, this would not exist by default unless CGROUP_RDT >> +is enabled. > > You can enable this just fine on AMD machines.
The cache alloc code is under CPU_SUP_INTEL ..
Thanks, Vikas
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